1. Field of the Invention
The present invention relates to a flash memory card with flash memory ICs mounted therein, which is suitable for use in a flash memory having a memory capacity of 4M bytes or more and is capable of performing a block erase operation.
2. Description of the Related Art
Mass-storage flash memories have been used in recent years as non-volatile auxiliary memories for a computer or the like. In a flash memory card having such memory ICs incorporated therein, the memories are erased on a block basis.
FIG. 6 is a view illustrating a configuration of a conventional flash memory IC. In the same drawing, there are shown a memory array 1, an X decoder 2 for performing decoding in an X direction of the memory array 1 from an address input, a Y decoder 3 for performing decoding in a Y direction of the memory array 1 from the address input, a Y gate 4, a sense amplifier/output buffer 5 used for the memory array 1, and a block address decoder 6 for designating a block address from the address input. The memory array 1 has a capacity of 8M bytes and is divided into sixteen 64K byte blocks. Write and erase operations can be carried out every blocks of the memory array 1.
Further, the flash memory IC is provided with a command user interface 7 for accepting and executing a command issued from a user, a write state machine 8 for controlling program (write) and erase operations, a status register 9 in which a state of the flash memory IC is written therein, and a chip-enable and output-enable circuit 10 for performing controls such as chip enable, output enable, etc. The command user interface 7 and the write state machine 8 perform an operation corresponding to the command issued from the user. The completion of the write or erase operation can be recognized by internally reading out the status register 9 or externally referring to ready/busy (RDY/BSY) terminals varied according to the state of the status register 9.
Further, when a signal of an "H" level is supplied to a Vpp terminal, write and block-erase operations can be performed. When a signal of an "L" level is supplied to a power down (PWD) terminal, the flash memory IC is brought to a deep power-down mode so that current consumption is extremely reduced. In the drawings employed in the present application, bars are respectively placed over the names of low active signals.
The block erase operation of the memory IC will now be described. FIG. 7 is a flowchart for describing the operation of the memory IC at the time of block erasure. The block erasure is executed as shown in the same drawing. Namely, a set-up command "20H" is written in a first cycle (Step S701) and an erase command "DOH" and a block address to be erased are written in the next cycle (Step S702). The block erasure is started by writing these data. When the memory IC is in the block erase operation, the inside of the memory IC is busy and hence program (write) and block-erase operations or the like cannot be executed on other blocks. However, if the reading of data from the memory is required (Step S704) even when the internal state of the memory IC is busy during the erase operation of the memory (Step S703), then the erase operation is temporarily suspended based on an erase suspend command (Step S705) and data about blocks other than the blocks which are in the erase suspend are read based on a read array command (Step S706). When the internal state of the memory IC is ready in Step S703, the completion of erasure can be confirmed by status polling for reading status register 9 or referring to the ready/busy (RDY/BSY) terminal. Thereafter, a program for the next block or an operation for erasing the next block is executed.
A flash memory card having the conventional block erasable flash memory ICs mounted therein will now be described. Each of flash memory ICs, which has a memory capacity of 4M bits or more, is normally provided with a block erasing function. Now, a flash memory card having 8M bit flash memory ICs mounted therein will be described below.
FIG. 8 is a view showing a configuration of a conventional flash memory card. In the same drawing, reference numeral 11 indicates a 68-pin connector for interfacing between systems based on PCMCIA2.0/JEIDA4.1 specifications. Reference numerals 12a, 12b, 12c, 12d, . . . respectively indicate block erasable flash memory ICs. Reference numeral 13 indicates an address control logic circuit for generating chip enable signals each indicative of a signal for selecting one of the flash memory ICs 12a, 12b, 12c, 12d, . . . to thereby designate an address for a memory IC to be accessed. Reference numeral 14 indicates a data control logic circuit for controlling the input of data therein and the outputting of it therefrom. The address control logic circuit 13 has an address buffer and a decode circuit incorporated therein. Further, the data control logic circuit 14 is provided with a data bus buffer and a data bus control circuit and controls the transfer of data between the internally-provided flash memory ICs.
FIG. 9 is a view for describing block structures for every device pairs of the flash memory ICs 12a, 12b, 12c, 12d, . . . As shown in the same drawing, each of the flash memory ICs is divided into sixteen 64K byte blocks. Upon data access, the address control logic circuit 13 selects any of a one-word access, a one-byte access and an odd-numbered byte access from a table shown in FIG. 10 according to a combination of "H" and "L" of signals CE1 and CE2. In the case of a mode (1) in FIG. 10, the eight lower order bits of 16-bit data given from the outside are taken in the flash memory card as one-byte data. In the case of a mode (2) as well, the eight higher order bits of the 16-bit data given from the outside are taken in the eight lower order bits on a data bus provided inside the flash memory card as one-byte data. Further, in the case of a mode (3), the 16-bit data given from the outside is taken in the flash memory card as one-word data. Furthermore, in the case of a mode (4), the eight higher order bits of the 16-bit data given from the outside are taken in the eight higher order bits on the data bus provided inside the flash memory card as one-byte data.
In the conventional flash memory card having the aforementioned block erasable flash memory ICs mounted therein, there is often a case in which block pairs are consecutively used as indicated by oblique lines in FIG. 9, for example. When consecutive areas of 64K words or more in the same device pair are erased, the address control logic circuit 13 first specifies a block pair address to enable a device pair including the areas indicated by the oblique lines. Next, 64K byte block pairs, which belong to the areas indicated by the oblique lines of the enabled device pair, are erased one by one. When such erasure is completed, the following block pair is erased. The completion of its erasure can be judged by checking whether an internal operating state is ready or busy. During the block erase operation, the internal state is busy and each device pair at the time of the internal state being busy, cannot be accessed. Thus, other blocks in the same device pair cannot be erased.
FIG. 11 is a view for describing output signals which appear at ready/busy terminals when a plurality of block pairs are erased. As shown in the same drawing, when one block pair is being erased, the ready/busy terminal is brought to "L", which shows a busy state. When the erase operation is completed, the ready/busy terminal is brought to "H" indicative of a ready state. The flash memory card enters into the next block pair erase operation when the ready/busy terminal is brought to "H." Therefore, when a plurality of block pairs are erased, the next block pair is erased as soon as the ready/busy terminal is brought to "H" upon erasing the previous block pair.
Therefore, the conventional flash memory card has a problem that when it is desired to erase the plurality of block pairs, the next block pair is erased after the ready/busy signal has been brought to "H" upon erasure of the previous block pair, thus requiring a lot of time for erasure of the block pairs.